Background

Programming

CPUs

  • Executes sequential bytes of machine code (instructions) each cycle

  • Clock speed (e.g., 4GHz) refers to the number of cycles/second

  • Registersarrow-up-right are fast (access time: <1 cycle), named values easily accessible in machine code. Extremely limited number (<32 per core)

  • The bitness (e.g., 64-bit) usually refers to the number of bits in a normal register

  • Main memoryarrow-up-right is slow (access time: 100s-10,000s cycles) and often difficult to access in machine code. Often 8-128GB total in a computer

  • An Instruction Set Architecturearrow-up-right (ISA) is an abstract model of a CPU describing supported instructions, available registers, and interactions with main memory E.g., x86-64arrow-up-right is the ISA Intel implements across its different concrete CPU hardware implementations

  • Assembly language targets a particular ISA, not a specific CPU

  • Complex Instruction setsarrow-up-right (CISC) perform many operations per instruction, variable byte count / instruction

    • For example: Load into register A from memory address in register X, multiple A by B, then add C

  • Reduced Instruction sets arrow-up-right(RISC) perform one operation per instruction, fixed byte count / instruction

    • For Example: Add register A to B

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